This invention relates to improved semiconductor devices and methods for their manufacture.
More particularly, this invention concerns semiconductor devices having an MOS IC structure with highly-doped low-resistance silicon film parts within a MOS insulation film and methods for manufacturing them.
Previously much research and development concerning MOS structures have been made. Taking as one representative example of such MOS semiconductor device, a silicon-gate MOS transistor is explained now referring to FIG. 1, wherein (a) is a plan view of the MOS transistor, (b) is a sectional front view seen at the sectional plane indicated by the line B-B' in (a), and (c) is a sectional sideview seen at the sectional plane indicated by the line C-C' in (a).
As shown in (a), (b) and (c) of FIG. 1, the MOS transistor is formed by the following steps:
On the semiconductor substrate 1, a thick SiO.sub.2 film as a field oxide film 2 and a thin SiO.sub.2 film as a gate oxide film 3, are formed by, for instance, the thermal oxidization method;
High-resistance polycrystalline silicon film is formed with a specified pattern so as to form gate region 5 and also cover selected regions;
Utilizing the polycrystalline silicon films as a mask, the part of silicon dioxide film 3, which part is not covered with the polycrystalline film, is etched away to expose the initial surface of the substrate from the windows 6, 7 formed by the etching;
An impurity is diffused through the windows 6, 7 to form the source region 8 and the drain region 9, respectively, and simultaneously, the polycrystalline silicon film 5 of low resistivity.
Thermal oxidation and SiO.sub.2 chemical vapor deposition (with SiH.sub.4 and O.sub.2 flowing on the wafer heated at about 400.degree. - 500.degree. C) form an SiO.sub.2 film 10 to cover the polycrystalline silicon films 5 of the gate; and
Three windows are formed on the SiO.sub.2 film 10, and contacts 12, 13, 14 for the source, the drain and the gate are made therethrough.
The merit of the abovementioned structure and making method is that the source and the drain regions can be formed by the so-called self-aligned diffusion process. However, the device and the method has a problem that, as seen in FIG. 1(c), in forming the contacts 12, 13 and 14 to the device, there occurs a difference in the level of the contacting plane on the polycrystalline silicon film, namely the sum of the thicknesses of the polycrystal silicon region 5 and the gate oxide film 3 to be etched way. Moreover, in forming the SiO.sub.2 film 10 on the polycrystalline silicon region 5 by the chemical vapor deposition method, the SiO.sub.2 film 10 usually becomes thicker on the region 5 than on other parts such as the field oxide films. This also serves to enhance the level or thickness difference. As a result of the high level differences, when other metallizations for interconnections are formed crosswise of the strip of the Si region 5 on FIG. 1(a), the metallized films tend to become thin at the step-shaped parts formed by the level difference, thereby increasing the possibility of breakdown of the connection. If a measure of thickening the metallization film to be greater than the thickness required to secure firm connections would be taken, the planview pattern of the device must be larger in size. Also, in such a prior art device, it has been necessary to form the diffused regions 8, 9 and the contact region 11a of polycrystalline Si 5 larger than the windows 11b, 11b and 11a in order to secure contact to the regions 8, 9 and 5, in the case of possible derangement of the mask registration. This also leads to an increase of the size of the device.
As has been mentioned above, the device and method of FIG. 1 has a drawback in that high density integration cannot be made on account of its large level differences in the surface structure. Furthermore, when etching the SiO.sub.2 films 2 and 10 to form the windows, there are possibilities of decreasing production yield of accidentally formed pin-holes on the CVD (chemically vapor-deposited) SiO.sub.2 film or on an etching mask.